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package half-bridge gate driver ic features ? floating channel up to +1200v ? soft overcurrent shutdown ? synchronization signal to synchronize shut down with the other phases ? integrated desaturation detection circuit ? two stage turn on output for di/dt control ? separate pull-up/pull-down output drive pins ? matched delay outputs ? under voltage lockout with hysteresis band www.irf.com 1 ir2214ss/ir22141ss 24-lead ssop v offset 1200v max. i o +/- (typ.) 2.0 a / 3.0a v out 10.4v - 20v deadtime matching (max) 75nsec deadtime (typ) 330nsec desat blanking time (typ) 3 sec dsh,dsl input voltage threshold (typ) 8.0v soft shutdown time (typ) 9.6 sec product summary description the ir2214ss/ir22141ss) is a gate driver suited to drive a single half bridge in power switching applications. the high gate driving capability (2a source, 3a sink) and the low quiescent current enable bootstrap supply techniques in medium power systems. the ir2214ss/ir22141ss driver features full short circuit protection by means of the power transistor desaturation detection. the ir2214ss/ir22141ss manages all the half-bridge faults by turning off smoothly the desaturated tran- sistor through the dedicated soft shut down pin, therefore preventing over-volt- ages and reducing em emissions. in multi-phase system ir2214ss/ir22141ss drivers communicate using a dedicated local network (sy_flt and fault/sd signals) to properly manage phase-to-phase short circuits. the system controller may force shutdown or read device fault state through the 3.3 v compatible cmos i/o pin (fault/sd). to improve the signal immunity from dc-bus noise, the control and power g round use dedicated pins enabling low-side emitter current sensing as well. under voltage conditions in floating and low voltage circuits are managed independently. typical connection (refer to lead assignments for correct pin configuration). this/ these diagram(s) show electrical connections only. please refer to our application notes and designtips for proper circuit board layout. data sheet no. pd60213 revb dc+ dc- dc bus (1200v) vcc lin hin fault/sd vb hop hon ssdh dsh vs lop lon ssdl dsl com vss ir2214 flt_clr sy_flt 15 v up, control motor ir2214ss/ir22141ss
2 ir2214/ir22141(ss) www.irf.com note 1: while internal circuitry is operational below the indicated supply voltages, the uv lockout disables the output drivers if the uv thresholds are not reached. note 2: logic operational for vs from vss-5 to vss+1200v. logic state held for vs from vss-5v to vss-vbs. (please refer to the design tip dt97-3 for more details). symbol definition min. max. units v b high side floating supply voltage (note 1) v s + 11.5 v s + 20 v s high side floating supply offset voltage note 2 1200 v ho high side output voltage (hop, hon and ssdh) v s v s + 20 v lo low side output voltage (lop, lon and ssdl) v com v cc v cc low side and logic fixed supply voltage (note 1) 11.5 20 com power ground - 5 5 v in logic input voltage (hin, lin and flt_clr) 0 v cc v flt fault input/output voltage (fault/sd and sy_flt) 0 v cc v dsh high side ds pin input voltage v b - 20 v b v dsl low side ds pin input voltage v cc - 20 v cc t a ambient temperature -40 125 c recommended operating conditions for proper operation the device should be used within the recommended conditions. all voltage parameters are absoute voltages referenced to v ss. the v s offset rating is tested with all supplies biased at 15v differential. v symbol definition min. max. units v s high side offset voltage v b - 25 v b + 0.3 v b high side floating supply voltage -0.3 1225 v ho high side floating output voltage (hop, hon and ssdh) v s - 0.3 v b + 0.3 v cc low side and logic fixed supply voltage -0.3 25 com power ground v cc - 25 v cc + 0.3 v lo low side output voltage (lop, lon and ssdl) v com -0.3 v cc + 0.3 v in logic input voltage (hin, lin and flt_clr) -0.3 v cc + 0.3 v flt fault input/output voltage (fault/sd and sy_flt) -0.3 v cc + 0.3 v dsh high side ds input voltage v b -25 v b + 0.3 v dsl low side ds input voltage v cc - 25 v cc + 0.3 dv s /dt allowable offset voltage slew rate ? 50 v/ns p d package power dissipation @ t a +25 c ? 1.5 w rth ja thermal resistance, junction to ambient ? 65 c/w t j junction temperature ? 150 t s storage temperature -55 150 t l lead temperature (soldering, 10 seconds) ? 300 absolute maximum ratings absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. all voltage parameters are absolute voltages referenced to v ss, all currents are defined positive into any lead the thermal resistance and power dissipation ratings are measured under board mounted and still air conditions. v c
3 ir2214/ir22141(ss) www.irf.com pin: v cc , v ss , v b , v s symbol definition min typ max units test conditions v ccuv+ vcc supply undervoltage positive going threshold 9.3 10.2 11.4 v ccuv- vcc supply undervoltage negative going threshold 8.7 9.3 10.3 v ccuvh vcc supply undervoltage lockout hysteresis - 0.9 - v bsuv+ (v b -v s ) supply undervoltage positive going threshold 9.3 10.2 11.4 v s =0v, v s =1200v v bsuv- (v b -v s ) supply undervoltage negative going threshold 8.7 9.3 10.3 v s =0v, v s =1200v v bsuvh (v b -v s ) supply undervoltage lockout hysteresis - 0.9 - v i lk offset supply leakage current - - 50 v b = v s = 1200v i qbs quiescent v bs supply current - 400 800 a v in = 0v or 3.3v i qcc quiescent vcc supply current - 0.7 2.5 ma (no load) v cc /v b v ccuv /v bsuv v ss /v s comparator uv internal signal figure 1: undervoltage diagram hin/lin/ fltclr v ss schmitt trigger 10k internal signal figure 2: hin, lin and fltclr diagram static electrical characteristics v cc = 15 v, v ss = com = 0 v, v s = 0 1200 v and t a = 25 o c unless otherwise specified. pin: hin, lin, fltclr, fault/sd, sy_flt symbol definition min typ max units test conditions v ih logic "1" input voltage 2.0 - - v il logic "0" input voltage - - 0.8 v ihss logic input hysteresis 0.2 0.4 - v v cc = v ccuv- to 20v i in+ logic "1" input bias current - 370 - a v in = 3.3v i in- logic "0" input bias current -1 - - v in = 0v r on,flt fault/sd open drain resistance - 60 - r on,sy sy_flt open drain resistance - 60 - ?
4 ir2214/ir22141(ss) www.irf.com the active bias is present only in ir22141. v desat , i ds and i dsb parameters are referenced to com and v s respectively for dsl and dsh. symbol definition min typ max units test conditions v desat+ high desat input threshold voltage 7.2 8.0 8.8 v desat- low desat input threshold voltage 6.3 7.0 7.7 v dsth desat input voltage hysteresis - 1.0 - v see fig. 16, 4 i ds+ high dsh or dsl input bias current - 21 - v desat = v cc or v bs i ds- low dsh or dsl input bias current - -160 - a v desat = 0v i dsb dsh or dsl input bias current (ir22141 only) - -20 - ma v desat = (v cc or v bs ) - 2v pin: dsl, dsh dsl/dsh v desat com/v s comparator 100k 700k v cc /v bs ssd internal signal active bias figure 4: dsh and dsl diagram fault/sd sy_flt v ss schmitt trigger r on fault/hold internal signal hard/soft shutdown internal signal figure 3: fault/sd and sy_flt diagram
5 ir2214/ir22141(ss) www.irf.com lop/hop v cc /v b on/off internal signal v oh 200ns oneshot figure 5: hop and lop diagram ssdl/ssdh com/v s on/off internal signal r on,ssd lon/hon desat internal signal v ol figure 6: hon, lon, ssdh and ssdl diagram pin: hop, lop symbol definition min typ max units test conditions v oh high level output voltage, v b ? v hop or v cc ?v lop - 20 100 mv i o = 1ma i o1+ output high first stage short circuit pulsed current - 2 - v hop/lop =0v, h in or l in = 1, pw?200ns, resistive load, see fig. 8 i o2+ output high second stage short circuit pulsed current - 1 - a v hop/lop =0v, h in or l in = 1, 400ns?pw?10s, resistive load, see fig. 8 40 300 20ma pin: hon, lon, ssdh, ssdl note 1: ssd operation only. symbol definition min typ ma x units test conditions v ol low level output voltage, v hon or v lon - 2.3 15 mv i o = 1ma r on,ssd soft shutdown on resistance (note 1) - 90 - ? 45 300 20ma 60
6 ir2214/ir22141(ss) www.irf.com ac electrical characteristics v cc = v bs = 15v, v s = v ss and t a = 25c unless otherwise specified. symbol definition min. typ. max. units test conditions ton turn on propagation delay 220 440 660 v in = 0 & 1 toff turn off propagation delay 220 440 660 v s = 0 to 1200v tr turn on rise time (c load =1nf) ? 24 ? hop shorted to hon, lop shorted to lon, tf turn off fall time (c load =1nf) ? 7 ? figure 7, 10 ton1 turn on first stage duration time 120 200 280 figure 8 t desat1 dsh to ho soft shutdown propagation delay at ho 2000 3300 4600 turn on v hin = 1 t desat2 dsh to ho soft shutdown propagation delay after 1050 ? ? v desat = 15v,fig.10 blanking t desat3 dsl to lo soft shutdown propagation delay at lo 2000 3300 4600 turn on v lin = 1 t desat4 dsl to lo soft shutdown propagation delay after 1050 ? ? v desat = 15v,fig.10 blanking t ds soft shutdown minimum pulse width of desat 1000 ? ? figure 9 t ss soft shutdown duration period 5000 9250 13500 c l =tbd f, v ds =15v,fig. 9 t sy_flt , dsh to sy_flt propagation delay at ho turn on ? 3600 ? desat1 v hin = 1 t sy_flt, dsh to sy_flt propagation delay after blanking 1300 ? ? v ds = 15v, fig. 10 desat2 t sy_flt, dsl to sy_flt propagation delay at lo turn on ? 3050 ? desat3 v lin = 1 t sy_flt, dsl to sy_flt propagation delay after blanking 1050 ? ? v desat =15v,fig.10 desat4 t bl ds blanking time at turn on ? 3000 ? v hin = v lin = 1 v desa t=15v,fig.10 dead-time/delay matching characteristics dt dead-time ? 330 ? figure 11 mdt dead-time matching, mdt=dth-dtl ? ? 75 external dt=0nsec figure 11 pdm propagation delay matching, ? ? 75 external dt> max(ton, toff) - min(ton, toff) ns 500nsec, fig.7 t v ds =15v, fig 9
7 ir2214/ir22141(ss) www.irf.com hin lin ho (hop=hon) lo (lop=lon) 10% 3.3v 10% 90% 90% 50% 50% t r t on t off t f pw in pw out figure 7: switching time waveforms ton1 io1+ io2+ figure 8: output source current
8 ir2214/ir22141(ss) www.irf.com hin/lin ho/lo v desat+ v desat- t ss t desat 3.3v dsh/dsl t ds ssd driver enable figure 9: soft shutdown timing waveform
9 ir2214/ir22141(ss) www.irf.com hin dsh sy_flt hon fault/sd fltclr lin lon dsl 50% 50% 50% 8v 8v 8v 8v 50% 50% 50% 50% 50% 90% 90% 50% 10% 90% 50% 90% 10% 90% 50% t on t bl softshutdown t desat1 t sy_flt,desat1 t bl t desat2 t sy_flt,desat2 softshutdown t on t bl t desat3 t sy_flt,desat3 softshutdown t bl t desat4 softshutdown t sy_flt,desat4 t off figure 10: desat timing hin lin ho (hop=hon) lo (lop=lon) dth dtl 50% 50% 50% 50% 50% mdt=dth-dtl 50% figure 11: internal dead-time timing
10 ir2214/ir22141(ss) www.irf.com symbol description vcc low side gate driver supply vss logic ground hin logic input for high side gate driver outputs (hop/hon) lin logic input for low side gate driver outputs (lop/lon) fault/sd dual function (in/out) active low pin. refer to figures 17, 18 and 15. as an output, indicates fault condition. as an input, shuts down the outputs of the gate driver regardless h in /l in status. sy_flt dual function (in/out) active low pin. refer to figures 17, 18 and 15. as an output, indicates ssd sequence is occurring. as an input, an active low signal freezes both output status. flt_clr fault clear active high input. clears latched fault condition (see figure 17) lop low side driver sourcing output lon low side driver sinking output dsl low side igbt desaturation protection input ssdl low side soft shutdown com low side driver return vb high side gate driver floating supply hop high side driver sourcing output hon high side driver sinking output dsh high side igbt desaturation protection input ssdh high side soft shutdown vs high side floating supply return lead definitions ssop24 1 12 24 13 ssdl flt_clr hin com sy_flt lon fault/sd vss lop vcc dsl hop ssdh hon n.c. vs n.c. dsh vb n.c. n.c. n.c. n.c. lin 24-lead ssop ? ir2214ss lead assignments
11 ir2214/ir22141(ss) www.irf.com functional block diagram schmitt trigger input shoot through prevention (dt) deadtime level shifters latch local desat protection soft shutdown uv_vbs detect di/dt control driver uv_vcc detect local desat protection softshutdown di/dt control driver on/off on/off desat soft shutdown on/off soft shutdown on/off (hs) desaths desatls on/off (ls) hard shutdown internal hold sd fault logic managemend (see figure 14) uv_vcc vb hop hon ssdh dsh vs lop lon ssdl dsl com vss flt_clr fault/sd sy_flt lin hin vcc fault hold ssd input hold logic output shutdown logic
12 ir2214/ir22141(ss) www.irf.com note1: a change of logic value of the signal labeled on lines (system variable) generates a state transition. note2: exiting from undervoltage v bs state, the ho goes high only if a rising edge event happens in h in . stable state ? fault ? ho=lo=0 (normal operation) ? ho/lo=1 (normal operation) ? undervoltage v cc ? shutdown (sd) ? undervoltage v bs ? freeze temporary state ? soft shutdown ? start up sequence system variable ? flt_clr ? hin/lin ? uv_vcc ? uv_vbs ? dsh/l ? sy_flt ? fault/sd start-up sequence fault ho/lo=1 ho=lo=0 undervoltage v cc ho=lo=0 freeze shutdown sy_flt sy_flt sy_flt flt_clr hin/lin hin/lin uv_vcc uv_vcc uv_vbs fault/sd dsh/l dsh/l fault/sd fault/sd fault/sd fault/sd uv_vbs uv_vcc desat event undervoltage v bs ho=0, lo=lin soft shutdown state diagram
13 ir2214/ir22141(ss) www.irf.com ho/lo status hop/lop hon/ lon ssdh/ssdl 0 hiz 0 hiz 1 1 hiz hiz ssd hiz hiz 0 lo/ho output follows inputs (in=1->out=1, in=0->out=0) lo n-1 /ho n-1 output keeps previous status ir2214 logic table note1: sy_flt automatically resets after ssd event is over and flt_clr is not required. in order to avoid flt_clr to conflict with the ssd procedure, flt_clr should not be operated while sy_flt is active. inputs input/output under voltage yes: v< uv threshold no : v> uv threshold x : don?t care outputs hin lin flt_clr sy_flt ssd: desat (out) hold: freezing (in) fault/sd sd: shutdown (in) fault: diagnostic (out) v cc v bs ho lo x x x x 0 (sd) x x 0 0 h in l in note1 (fault) no no ho lo 1 0 0 1 1 no no 1 0 0 1 0 1 1 no no 0 1 0 0 0 1 1 no no 0 0 1 1 0 1 1 no no 0 0 1 0 0 (ssd) 1 no no ssd 0 0 1 0 (ssd) 1 no no 0 ssd x x 0 (ssd) (fault) no no 0 0 x x 0 (ssd) (fault) no no 0 0 x x x 0 (hold) 1 no no ho n-1 lo n-1 x l in x 1 1 no yes 0 lo x x x 1 0 (fault) yes x 0 0 normal operation anti shoot through soft shut down (entering) soft shut down (finishing) freeze shut down fault clear operation under voltage output drivers status description
14 ir2214/ir22141(ss) www.irf.com features description 1. start-up sequence at power supply start-up it is recommended to keep flt_clr pin active until supply voltages are properly established. this prevents spurious diagnostic signals being generated. all protection functions are operating independently from flt_clr status and output driver status reflects the input commands. when bootstrap supply topology is used for supplying the floating high side stage, the following start-up sequence is recommended (see also figure 12): 1. set vcc 2. set flt_clr pin to high level 3. set lin pin to high level and let the bootstrap capacitor be charged 4. release lin pin to low level 5. release flt_clr pin to low level figure 12 start-up sequence a minimum 15 s lin and flt-clr pulse is required. vcc flt_clr lin lo 2. normal operation mode after start-up sequence has been terminated, the device becomes fully operative (see grey blocks in the state diagram). hin and lin produce driver outputs to switch accordingly, while the input logic checks the input signals preventing shoot-through events and including deadtime (dt). 3. shut down the system controller can asynchronously command the hard shutdown (hsd) through the 3.3 v compatible cmos i/o fault/sd pin. this event is not latched. in a multi-phase system, fault/sd signals are or-wired so the controller or one of the gate drivers can force simultaneous shutdown to the other gate drivers through the same pin. 4. fault management ir2214 is able to manage both the supply failure (undervoltage lock out on both low and high side circuits) and the desaturation of both power transistors. 4.1 undervoltage (uv) the undervoltage protection function disables the driver?s output stage preventing the power device being driven with too low voltages. both the low side (v cc supplied) and the floating side (v bs supplied) are controlled by a dedicate undervoltage function. undervoltage event on the v cc (when v cc < uv vcc- ) generates a diagnostic signal by forcing fault/sd pin low (see fault/sd section and figure 14). this event disables both low side and floating drivers and the diagnostic signal holds until the under voltage condition is over. fault condition is not latched and the fault/sd pin is released once v cc becomes higher than uv vcc+ .
15 ir2214/ir22141(ss) www.irf.com the undervoltage on the v bs works disabling only the floating driver. undervoltage on v bs does not prevent the low side driver to activate its output nor generate diagnostic signals. v bs undervoltage condition (v bs < uv vbs- ) latches the high side output stage in the low state. v bs must be reestablished higher than uv vbs+ to return in normal operating mode. to turn on the floating driver h in must be re-asserted high (rising edge event on h in is required). 4.2 power devices desaturation different causes can generate a power inverter failure: phase and/or rail supply short-circuit, overload conditions induced by the load, etc? in all these fault conditions a large current increase is produced in the igbt. the ir2214 fault detection circuit monitors the igbt emitter to collector voltage (v ce ) by means of an external high voltage diode. high current in the igbt may cause the transistor to desaturate, i.e. v ce to increase. once in desaturation, the current in power transistor can be as high as 10 times the nominal current. whenever the transistor is switched off, this high current generates relevant voltage transients in the power stage that need to be smoothed out in order to avoid destruction (by over-voltages). the ir2214 gate driver accomplish the transients control by smoothly turning off the desaturated transistor by means of the ssd pin activating a so called soft shutdown sequence (ssd). 4.2.1 de sa tu r atio n de te ctio n: dsh/l func tio n figure 13 shows the structure of the desaturation sensing and soft shutdown block. this configu- ration is the same for both high and low side output stages. figure 13: high and low side output stage t bl blanking vb/vcc hon/lon dsh/l vs/com ron,ss hop/lop tss one shot v desat (t on 1) one shot t ds filter ssdh/l rdsh/l p p r r e e d d r r i i v v e e r r sensing diode on/off desaths/ls desat comparator
16 ir2214/ir22141(ss) www.irf.com fltclr q q set clr s r fault/sd sy_flt internal hold (external hold) (external hard shutdown) internal fault (hard shutdown) uvcc desaths desatls figure 14 : fault management diagram the external sensing diode should have bv>1200v and low stray capacitance (in order to minimize noise coupling and switching de- lays). the diode is biased by an internal pull-up resistor r dsh/l (equal to v cc /i ds- or v bs /i ds- for ir2214) or by a dedicated circuit (see the active- bias section for the ir22141). when v ce in- creases, the voltage at dsh/l pin increases too. being internally biased to the local supply, dsh/l voltage is automatically clamped. when dsh/l exceeds the v desat+ threshold the com- parator triggers (see figure 13). comparator output is fil tered in order to avoid false desaturation detection by externally induced noise; pulses shorter than t ds are filtered out. to avoid detecting a false desaturation during igbt turn on, the desaturation circuit is disabled by a blanking signal (t bl , see blanking block in fig- ure 13). this time is the estimated maximum igbt turn on time and must be not exceeded by proper gate resistance sizing. when the igbt is not completely saturated after t bl , desaturation is detected and the driver will turn off. eligible desaturation signals initiate the soft shutdown sequence (ssd). while in ssd, the output driver goes in high impedance and the ssd pull-down is activated to turn off the igbt through ssdh/l pin. the sy_flt output pin (active low, see figure 14) reports the ir2214 status all the way long ssd sequence lasts (t ss ). once finished ssd, sys_flt releases, and ir2214 generates a fault signal (see the fault/sd section) by activating fault/sd pin. this generates a hard shut down for both high and low output stages (ho=lo=low). each driver is latched low until the fault is cleared (see flt_clr). figure 14 shows the fault management circuit. in this diagram desaths and desatls are two internal signals that come from the output stages (see figure 13).
17 ir2214/ir22141(ss) www.irf.com it must be noted that while in soft shut down, both under voltage fault and external shut down (sd) are masked until the end of ssd. desaturation protection is working independently by the other entire control pin and it is disabled only when the output status is off. vcc lin hin flt_clr vb hop hon ssh dsh vs lop lon ssl dsl com vss sy_flt fault/sd ir2214 vcc lin hin flt_clr vb hop hon ssh dsh vs lop lon ssl dsl com vss sy_flt fault/sd ir2214 vcc lin hin flt_clr vb hop hon ssh dsh vs lop lon ssl dsl com vss sy_flt fault/sd ir2214 phase u phase v phase w fault 4.2.2 fault management in multi-phase systems in a system with two or more gate drivers the ir2214 devices must be connected as in figure 15. sy_fl t . the bi-directional sy_flt pins communicate each other in the local network. the logic signal is active low. the device that detects the igbt desaturation activates the sy_flt, which is then read by the other gate drivers. when sys_flt is active all the drivers hold their output state regardless the input signals (h in , l in ) they receive from the controller (freeze state). this feature is particularly important in phase- to-phase short circuit where two igbts are involved; in fact, while one is softly shutting-down, the other must be prevented from hard shutdown to avoid vanishing ssd. in the freeze state the frozen drivers are not completely inactive because desaturation detection still takes the highest priority. sy_flt communication has been designed for creating a local network between the drivers. there is no need to wire sy_flt to the controller. f aul t/sd the bi-directional fault/sd pins communicates each other and with the system controller. the logic signal is active low. when low, the fault/sd signal commands the outputs to go off by hard shutdown. there are three events that can force fault/sd low: 1. desaturation detection event: the fault\sd pin is latched low when ssd is over, and only a flt_clr signal can reset it. figure 15: ir2214 application in 3ph system.
18 ir2214/ir22141(ss) www.irf.com 2. undervoltage on v cc : the fault\sd pin is forced low and held until the undervoltage is active ( not latched ). 3. fault/sd is externally driven low either from the controller or from another ir2214 device. this event is not latched ; therefore the flt_clr cannot disable it. only when fault/sd becomes high the device returns in normal operating mode. 5. active bias for the purpose of sensing the power transistor desaturation the collector voltage is read by an external hv diode. the diode is normally biased by an internal pull up resistor connected to the local supply line (v b or v cc ). when the transistor is ?on? the diode is conducting and the amount of current flowing in the circuit is determined by the internal pull up resistor value. in the high side circuit, the desaturation biasing current may become relevant for dimensioning the bootstrap capacitor (see figure 19). in fact, too low pull up resistor value may result in high current discharging significantly the bootstrap capacitor. for that reason typical pull up resistor are in the range of 100 k . this is the value of the internal pull up. while the impedance of dsh/dsl pins is very low when the transistor is on (low impedance path through the external diode down to the power transistor), the impedance is only controlled by the pull up resistor when the transistor is off. in that case relevant dv/dt applied by the power transistor during the commutation at the output results in a considerable current injected through the stray capacitance of the diode into the desaturation detection pin (dsh/l). this coupled noise may be easily reduced using an active bias for the sensing diode. an active bias structure is available only for ir22141 version for dsh/l pin. the dsh/l pins present an active pull-up respectively to vb/vcc, and a pull-down respectively to vs/com. the dedicated biasing circuit reduces the impedance on the dsh/l pin when the voltage exceeds the v desat threshold (see figure 16). this low impedance helps in rejecting the noise providing the current inject by the parasitic capacitance. when the power transistor is fully on, the sensing diode gets forward biased and the voltage at the dsh/l pin decreases. at this point the biasing circuit deactivates, in order to reduce the bias current of the diode as shown in figure 16. figure 16: r dsh/l active biasing 6. output stage the structure is shown in figure 13 and consists of two turns on stages and one turn off stage. when the driver turns on the igbt (see figure 8), a first stage is constantly activated while an additional stage is maintained active only for a limited time (ton1). this feature boost the total driving capability in order to accommodate both fast gate charge to the plateau voltage and dv/dt control in switching. v dsh/l v desat- v desat+ 100 ohm 100k ohm r dsh/l
19 ir2214/ir22141(ss) www.irf.com at turn off, a single n-channel sinks up to 3a (i o- ) and offers a low impedance path to prevent the self-turn on due to the parasitic miller capacitance in the power switch. hin lin fault/sd lo(lop/lon) dsh flt_clr sy_flt ho(hop/hon) dsl a b c d e f g figure 17: i/o timing diagram with sy_flt and fault/sd as output 7. timing and logic state diagrams description the following figures show the input/output logic diagram. figure 17 shows the sy_flt and fault/sd signals as output, whereas figure 18 shows them as input.
20 ir2214/ir22141(ss) www.irf.com ab c d e f hin lin sy_flt fault/sd flt_clr ho (hop/hon) lo (lop/lon) figure 18: i/o logic diagram with sy_flt and fault/sd as input referred to timing diagram of figure 17: a. when the input signals are on together the outputs go off (anti-shoot through). b. the ho signal is on and the high side igbt desaturates, the ho turn off softly while the sy_flt stays low. when sy_flt goes high the fault/sd goes low. while in ssd, if lin goes up, lo does not change (freeze). c. when fault/sd is latched low (see fault/ sd section) flt_clr can disable it and the outputs go back to follow the inputs. d. the dsh goes high but this is not read because ho is off. e. the lo signal is on and the low side igbt desaturates, the low side behaviour is the same as described in point b. f. the dsl goes high but this is not read because lo is off. g. as point a (anti-shoot through). referred to logic diagram figure 18: a. the device is in hold state, regardless of input variations. hold state is forced by sy_flt forced low externally b. the device outputs goes off by hard shutdown, externally commanded. a through b is the same sequence adopted by another ir2214 device in ssd procedure. c. externally driven low fault/sd (shutdown state) cannot be disabled by forcing flt_clr (see fault/sd section). d. the fault/sd is released and the outputs go back to follow the inputs. e. externally driven low fault/sd: outputs go off by hard shutdown (like point b). f. as point a and b but for the low side output.
21 ir2214/ir22141(ss) www.irf.com sizing tips bootstrap supply the v bs voltage provides the supply to the high side driver circuitry of the ir2214. this supply sits on top of the v s voltage and so it must be floating. the bootstrap method to generate v bs supply can be used with ir2214. the bootstrap supply is formed by a diode and a capacitor connected as in figure 19. figure 19: bootstrap supply schematic this method has the advantage of being simple and low cost but may force some limitations on duty-cycle and on-time since they are limited by the requirement to refresh the charge in the boot- strap capacitor. proper capacitor choice can reduce drastically these limitations. bootstrap capacitor sizing to size the bootstrap capacitor, the first step is to establish the minimum voltage drop ( v bs ) that we have to guarantee when the high side igbt is on. bootstrap diode ir2214 bootstrap capacitor vb vs vcc hop hon ssdh dc+ bootstrap resistor com v cc v bs v f v ge v ceon v fp i load motor r boot if v gemin is the minimum gate emitter voltage we want to maintain, the voltage drop must be: under the condition: where v cc is the ic voltage supply, v f is boot- strap diode forward voltage, v ceon is emitter-col- lector voltage of low side igbt and v bsuv- is the high-side supply undervoltage negative going threshold. now we must consider the influencing factors contributing v bs to decrease: - igbt turn on required gate charge ( q g ); - igbt gate-source leakage current ( i lk_ge ); - floating section quiescent current ( i qbs ); - floating section leakage current ( i lk ) - bootstrap diode leakage current ( i lk_diode ); - desat diode bias when on ( i ds- ) - charge required by the internal level shifters ( q ls ); typical 20nc - bootstrap capacitor leakage current ( i lk_cap ); - high side on time ( t hon ). i lk_cap is only relevant when using an electrolytic capacitor and can be ignored if other types of capacitors are used. it is strongly recommend using at least one low esr ceramic capacitor (paralleling electrolytic and low esr ceramic may result in an efficient solution). then we have: ceon ge f cc bs v v v v v ? ? ? min ? > bsuv ge v v min + + + + = qbs ge lk ls g tot i i q q q _ ( hon ds cap lk diode lk lk t i i i i + + + + ? ) _ _
22 ir2214/ir22141(ss) www.irf.com the minimum size of bootstrap capacitor is: an example follows: a) using a 25a @ 125c igbt (irgp30b120kd): ? i qbs = 800 a (see static electrical charact.); ? i lk = 50 a (see static electrical charact.); ? q ls = 20 nc; ? q g = 160 nc (datasheet irgp30b120kd); ? i lk_ge = 100 na (datasheet irgp30b120kd); ? i lk_diode = 100 a (with reverse recovery time <100 ns); ? i lk_cap = 0 (neglected for ceramic capacitor); ? i ds- = 150 a (see static electrical charact.); ? t hon = 100 s. and: ? v cc = 15 v ? v f = 1 v ? v ceonmax = 3.1 v ? v gemin = 10.5 v the maximum voltage drop v bs becomes and the boodstrap capacitor is: bs tot boot v q c = min = ? ? ? ceon ge f cc bs v v v v v min v v v v v 4 . 0 1 . 3 5 . 10 1 15 = ? ? ? = nf v nc c boot 725 4 . 0 290 = notice: here above v cc has been cho- sen to be 15v. some igbts may require higher supply to work correctly with the boot- strap technique. also vcc variations must be accounted in the above formulas. some important considerations a. v oltage ripple there are three different cases making the boot- strap circuit gets conductive (see figure 19): ? i load < 0; the load current flows in the low side igbt displaying relevant v ceon in this case we have the lowest value for v bs . this represents the worst case for the bootstrap capacitor sizing. when the igbt is turned off the vs node is pushed up by the load current until the high side freewheeling diode get for- warded biased ? i load = 0; the igbt is not loaded while be- ing on and v ce can be neglected ? i load > 0; the load current flows through the freewheeling diode in this case we have the highest value for v bs . turning on the high side igbt, i load flows into it and v s is pulled up. to minimize the risk of undervoltage, bootstrap capacitor should be sized according to the i load <0 case. ceon f cc bs v v v v ? ? = f cc bs v v v ? = fp f cc bs v v v v + ? =
23 ir2214/ir22141(ss) www.irf.com b. bootstrap resistor a resistor (r boot ) is placed in series with boot- strap diode (see figure 19) so to limit the current when the bootstrap capacitor is initially charged. we suggest not exceeding some ohms (typi- cally 5, maximum 10 ohm) to avoid increasing the v bs time-constant. the minimum on time for charging the bootstrap capacitor or for refresh- ing its charge must be verified against this time- constant. c. bootstrap capacitor for high t hon designs where is used an electro- lytic tank capacitor, its esr must be consid- ered. this parasitic resistance forms a voltage divider with r boot generating a voltage step on v bs at the first charge of bootstrap capacitor. the voltage step and the related speed (dv bs /dt) should be limited. as a general rule, esr should meet the following constraint: parallel combination of small ceramic and large electrolytic capacitors is normally the best com- promise, the first acting as fast charge thank for the gate charge only and limiting the dv bs /dt by reducing the equivalent resistance while the sec- ond keeps the v bs voltage drop inside the de- sired v bs . d. bootstrap diode the diode must have a bv> 1200v and a fast recovery time (trr < 100 ns) to minimize the amount of charge fed back from the bootstrap capacitor to v cc supply v v r esr esr cc boot 3 + gate resistances the switching speed of the output transistor can be controlled by properly size the resistors con- trolling the turn-on and turn-off gate current. the following section provides some basic rules for sizing the resistors to obtain the desired switch- ing time and speed by introducing the equivalent output resistance of the gate driver ( r drp and r drn ). the examples always use igbt power transis- tor. figure 20 shows the nomenclature used in the following paragraphs. in addition, v ge * indi- cates the plateau voltage, q gc and q ge indicate the gate to collector and gate to emitter charge respectively. figure 20: nomenclature v ge * 10% t 1 ,q ge c resoff c reson v ce i c v ge c res 10% 90% c res t don v ge dv/dt i c t 2 ,q gc t,q t r t sw
24 ir2214/ir22141(ss) www.irf.com >

? + = + + + 1 1 1 1 2 1 1 1 on sw o on sw on sw o o sw on drp t t when i vcc t t when t t i vcc i vcc t t r when r gon > 7 ohm, r drp is defined by (i o1+ ,i o2+ and t on1 from the ir2214 datasheet). resoff avg out c i dt dv = table 1 reports the gate resistance size for two commonly used igbts (calculation made using typical datasheet values and assuming vcc=15v). ? output voltage slope turn-on gate resistor r gon can be sized to con- trol output slope (dv out /dt) . while the output voltage has a non-linear behaviour, the maximum output slope can be ap- proximated by: inserting the expression yielding i avg and rearranging: as an example, table 2 shows the sizing of gate resistance to get dv out /dt=5v/ns when using two popular igbts, typical datasheet values and assuming vcc=15v . notice : turn on time must be lower than t bl to avoid improper desaturation detection and ssd triggering. dt dv c v vcc r out resoff ge tot ? = * sizing the turn-on gate resistor ? switching-time for the matters of the calculation included here- after, the switching time t sw is defined as the time spent to reach the end of the plateau voltage (a total q gc + q ge has been provided to the igbt gate). to obtain the desired switching time the gate resistance can be sized starting from q ge and q gc , vcc , v ge * (see figure 21): and figure 21: r gon sizing sw ge gc avg t q q i + = vcc/vb r drp r gon c res com/vs i avg where gon drp tot r r r + = r gon = gate on-resistor r dr p = driver equivalent on-resistance avg ge tot i v vcc r * ? =
25 ir2214/ir22141(ss) www.irf.com off hs turning on on dv/dt r goff c resoff r drn translated into equations:: rearranging the equation yields: when r goff > 4 ohm, r drn is well defined by vcc/i o- (i o- from ir2214 datasheet). as an example, table 3 reports r goff for two popu- lar igbt to withstand dv out /dt = 5v/ns . notice: the above-described equations are in- tended being an approximated way for the gate resistances sizing. more accurate sizing may account more precise device modelling and para- sitic component dependent on the pcb and power section layout and related connections. ()() r r i r r v drn goff drn goff th + = + dt dv c out resoff drn resoff th goff r dt dv c v r ? sizing the turn-off gate resistor the worst case in sizing the turn-off resistor r goff is when the collector of the igbt in off state is forced to commutate by external events (i.e. the turn-on of the companion igbt). in this case the dv/dt of the output node induces a parasitic current through c resoff flowing in r goff and r drn (see figure 22). if the voltage drop at the gate exceeds the thresh- old voltage of the igbt, the device may self turn on causing large oscillation and relevant cross conduction. figure 22: r goff sizing: current path when low side is off and high side turns on igbt qge qgc vge* tsw iavg rtot rgon std commercial value tsw irgp30b120k(d) 19nc 82nc 9v 400ns 0.25a 24 rtot - rdrp = 12.7 ? ? ? ? igbt qge qgc vge* cresoff rtot rgon std commercial value dvout/dt irgp30b120k(d) 19nc 82nc 9v 85pf 14 rtot - rdrp = 6.5 ? ? ? ? igbt vth(min) cresoff rgoff irgp30b120k(d) 4 85pf rgoff ? 4 ? ? table 1: t sw driven r gon sizing table 2: dv out /dt driven r gon sizing table 3: r goff sizing
26 ir2214/ir22141(ss) www.irf.com pcb layout tips distance from h to l voltage : the ir2214 pin out maximizes the distance be- tween floating (from dc- to dc+) and low voltage pins. it?s strongly recommended to place com- ponents tied to floating voltage in the high volt- age side of device (v b , v s side) while the other components in the opposite side. ground plane: ground plane must not be placed under or nearby the high voltage floating side to minimize noise coupling. gate drive loops: current loops behave like an antenna able to re- ceive and transmit em noise. in order to reduce em coupling and improve the power switch turn on/off performances, gate drive loops must be reduced as much as possible. figure 23 shows the high and low side gate loops. moreover, current can be injected inside the gate drive loop via the igbt collector-to-gate parasitic capacitance. the parasitic auto-inductance of the gate loop contributes to develop a voltage across the gate-emitter increasing the possibility of self turn-on effect. for this reason is strongly recom- mended to place the three gate resistances close together and to minimize the loop area (see figure 23). gate resistance vs/com vb/ vcc h/lop h/lon ssdh/l v ge gate drive loop c gc i gc figure 23 : gate drive loop supply capacitors: ir2214 output stages are able to quickly turn on igbt with up to 2 a of output current. the sup- ply capacitors must be placed as close as pos- sible to the device pins (v cc and v ss for the ground tied supply, v b and v s for the floating supply) in order to minimize parasitic inductance/ resistance. routing and placement example: figure 24 shows one of the possible layout solu- tions using a 3 layer pcb. this example takes into account all the previous considerations. placement and routing for supply capacitors and gate resistances in the high and low voltage side minimize respectively supply path and gate drive loop. the bootstrap diode is placed under the device to have the cathode as close as possible to bootstrap capacitor and the anode far from high voltage and close to v cc .
27 ir2214/ir22141(ss) www.irf.com referred to figure 24: bootstrap section: r1, c1, d1 high side gate: r2, r3, r4 high side desat: d2 low side supply: c2 low side gate: r5, r6, r7 low side desat: d3 r2 r3 r4 r5 r6 r7 c2 d3 d2 ir2214 v gh v gl dc+ phase a) b) d1 r1 c1 v eh v el v cc c) figure 24: layout example: top (a), bottom (b) and ground plane (c) layer
28 ir2214/ir22141(ss) www.irf.com ir world headquarters: 233 kansas st., el segundo, california 90245 tel: (310) 252-7105 his poduct has been designed and uaified fo the ndustia aet data and specifications subject to change without notice. 1/26/ 2005 ase outine 01 0 01 01 55 01 150 2ead

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